A circuit for the speed recovery of a direct current motor includes an output stage, output stage having a first pair of transistors, a second pair of transistors, and means a first circuit configured to detect a current circulating in the motor. The output stage further includes a second circuit configured to, activate the second pair transistors for a determined first time period so as to short-circuit the motor, and, at the end of the first time period, unbalance the output stage so as to force a maximum current to circulate for a determined second time period as a function of a value detected by the first circuit during the first time period, so as to stop the motor.