发明授权
- 专利标题: Interrupt control apparatus and method separately holding respective operation information of a processor preceding a normal or a break interrupt
- 专利标题(中): 中断控制装置和方法分别保持处理器在正常或中断中断之前的相应操作信息
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申请号: US09678732申请日: 2000-10-04
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公开(公告)号: US06681280B1公开(公告)日: 2004-01-20
- 发明人: Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
- 申请人: Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
- 优先权: JP11-309598 19981029; JP11-341077 19991130
- 主分类号: G06F1324
- IPC分类号: G06F1324
摘要:
When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.
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