Invention Grant
- Patent Title: Semiconductor memory having electrically erasable and programmable semiconductor memory cells
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Application No.: US10304046Application Date: 2002-11-26
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Publication No.: US06683812B2Publication Date: 2004-01-27
- Inventor: Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
- Applicant: Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
- Priority: JP9-139019 19970528
- Main IPC: G11C700
- IPC: G11C700

Abstract:
A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell. As a result of these operations, the semiconductor memory can determine the pieces of bit data in the order of the buffer A and the buffer B every time the discriminating operation is performed with respect to the cell.
Public/Granted literature
- US20030072203A1 Semiconductor memory having electrically erasable and programmable semiconductor memory cells Public/Granted day:2003-04-17
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