发明授权
- 专利标题： Configuration for identifying contact faults during the testing of integrated circuits
- 专利标题（中）： 在集成电路测试期间识别接触故障的配置
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申请号： US09277281申请日： 1999-03-26
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公开(公告)号： US06693447B1公开(公告)日： 2004-02-17
- 发明人: Dominique Savignac , Frank Weber , Norbert Wirth
- 申请人： Dominique Savignac , Frank Weber , Norbert Wirth
- 优先权： DE19813503 19980326
- 主分类号： G01R3126
- IPC分类号： G01R3126
摘要：
A configuration for identifying contact faults during the testing of integrated circuits with a multiplicity of pins which protrude from a housing and are connected to respective pads on a semiconductor body of the integrated circuit. Pull-up or pull-down devices are connected between respective pads and input buffers and in each case hold the pads at a high or low potential by impressing a holding current, if contact has not been made with a pin associated with the pad during testing, the result being that activation of the circuit section connected to the pin is avoided.
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