A DRAM cell is provided, along with a method for fabricating such a DRAM cell. A protection layer pattern is formed to cover a common drain region of first and second access transistors. Storage node holes are then formed to expose each source region of the first and second access transistors, by using an etching insulator that has an etching selectivity with respect to the protection layer. Accordingly, even if there is a misalignment of the storage node holes to the source regions, the common drain region is not exposed by the misaligned storage node holes because of the presence of the protection layer pattern.