A manufacturing method of flash memory. A substrate is provided, on which a gate structure is formed. A first spacer is formed on the sidewalls of the gate structure. A source region is formed in the substrate at one side of the gate structure. A first conductive layer and a sacrificial layer are formed on the substrate. The first conductive layer and the sacrificial layer are removed until the gate structure is exposed. A thermal oxidation process is performed to form a mask layer on the first conductive layer and the gate structure. The sacrificial layer remaining on the first conductive layer is removed, and the first conductive layer is etched with a square shape. The mask layer is removed, and a second spacer is formed on the sidewalls of the second conductive layer. A drain region is formed in the substrate at one side of the conductive layer.