A method of forming an integrated circuit transistor (80), comprising providing a semiconductor region (90) and forming a gate structure (92, 94) in a fixed position relative to the semiconductor region. The gate structure has a first sidewall (94a) and a second sidewall (94b). The method also comprises first, forming a first layer (96) adjacent the first sidewall and the second sidewall, and second, forming a second layer (98) adjacent the first layer. The method also comprises third, forming a third layer (100) adjacent the second layer, and fourth, forming a fourth layer (102) adjacent the third layer. The method also comprises fifth, implanting a first and second source/drain region (106a, 106b) in the semiconductor region and at a first distance laterally with respect to the gate structure, wherein a combined thickness of the first, second, third, and fourth layers determines the first distance. The method also comprises sixth, removing the third and fourth layers, and seventh, implanting a third and fourth source/drain region (108a, 108b) in the semiconductor region and at a second distance laterally with respect to the gate structure, wherein the second distance is less than the first distance.