A microprocessor core 4 is modeled using an obscured model 22 of the core functionality and a non-obscured model 24 of the scan chains that in that particular instance are associated with the microprocessor core 4. Validation of the design of a scan chain controller 12 can be achieved using the non-obscured scan chain model 24. Different scan chain models 24 can be relatively easily provided to model different scan chain physical configurations whilst leaving the more difficult to produce obscured core model 22 unaltered.