A drive circuit including circuitry that can be easily adjusted, the output drive current can be kept balanced, and high-precision drive current can be supplied to the load circuit. Clamp circuit 10 is furnished to hold the drain voltage of current output transistor QN12, which supplies drive current to a load resistor. When transistor QN12 is in a conducting state, drain voltage VA of transistor QN12 is held at approximately the same level as source voltage VD of transistor QN14 by clamp circuit 10. So rise and fall in the drain output current of transistor QN12 can be kept balanced, and rise and fall delay time can be made approximately equal for input signal Sin.