利索-全球专利检索

  1. 登录
  2. 注册
发明授权
US06710732B1 Three-state binary adders with endpoint correction and methods of operating the same 有权
具有端点校正的三态二进制加法器和操作方法相同

  • 专利标题： Three-state binary adders with endpoint correction and methods of operating the same
  • 专利标题（中）： 具有端点校正的三态二进制加法器和操作方法相同
  • 申请号： US09569955
    申请日： 2000-05-12
  • 公开(公告)号： US06710732B1
    公开(公告)日： 2004-03-23
  • 发明人: Arlo J. Aude
  • 申请人： Arlo J. Aude
  • 主分类号： H03M112
  • IPC分类号： H03M112
Three-state binary adders with endpoint correction and methods of operating the same
摘要：
Three-state binary adders with endpoint correction are employed in a digital signal processing system within a pipelined analog-to-digital converter. The adder is operable to add received signals. The endpoint correction circuitry, which is associated with the adder, is operable to (i) use ±½ full scale tip voltages and to (ii) generate over and under indicators.
摘要（中）：

在流水线模数转换器中的数字信号处理系统中采用具有端点校正的三态二进制加法器。 加法器可操作以添加接收的信号。 与加法器相关联的端点校正电路可操作为（i）使用±½满量程尖端电压，并且（ii）产生超过和低于指示器。

信息查询
Espacenet
0/0