发明授权
- 专利标题: Memory architecture with write circuitry and method therefor
- 专利标题(中): 具有写入电路的存储器架构及其方法
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申请号: US10185888申请日: 2002-06-28
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公开(公告)号: US06714440B2公开(公告)日: 2004-03-30
- 发明人: Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
- 申请人: Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
- 主分类号: G11C1100
- IPC分类号: G11C1100
摘要:
A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.