发明授权
US06715057B1 Efficient translation lookaside buffer miss processing in computer systems with a large range of page sizes
失效
具有大范围页面大小的计算机系统中的高效翻译后备缓冲区丢失处理
- 专利标题: Efficient translation lookaside buffer miss processing in computer systems with a large range of page sizes
- 专利标题(中): 具有大范围页面大小的计算机系统中的高效翻译后备缓冲区丢失处理
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申请号: US09652552申请日: 2000-08-31
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公开(公告)号: US06715057B1公开(公告)日: 2004-03-30
- 发明人: Richard E. Kessler , Jeffrey G. Wiedemeier , Eileen J. Samberg
- 申请人: Richard E. Kessler , Jeffrey G. Wiedemeier , Eileen J. Samberg
- 主分类号: G06F1210
- IPC分类号: G06F1210
摘要:
A system and method is disclosed to efficiently translate virtual-to-physical addresses of large size pages of data by eliminating one level of a multilevel page table. A computer system containing a processor includes a translation lookaside buffer (“TLB”) in the processor. The processor is connected to a system memory that contains a page table with multiple levels. The page table translates the virtual address of a page of data stored in system memory into the corresponding physical address of the page of data. If the size of the page is above a certain threshold value, then translation of the page using the multilevel page table occurs by eliminating one or more levels of the page table. The threshold value preferably is 512 Megabytes. The multilevel page table is only used for translation of the virtual address of the page of data stored in system memory into the corresponding physical address of the page of data if a lookup of the TLB for the virtual address of the page of data results in a miss. The TLB also contains entries from the final level of the page table (i.e., physical addresses of pages of data) corresponding to a subfield of bits from corresponding virtual addresses of the page of data. Virtual-to-physical address translation using the multilevel page table is not required if the TLB contains the needed physical address of the page of data corresponding to the subfield of bits from the virtual address of the page of data.
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