A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or verify operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the verify logic initiates verify routine in response to an event such as an operator instruction, hot-plug operation, or a periodic schedule. By implementing the verify operation, the system does not rely on external READ commands to verify data integrity. The verify routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the verify routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.