In an array of integrated transistor/memory structures the array includes one or more layers of semiconducting material, two or more electrode layers, and memory material contacting electrodes in the latter. At least one layer of a semiconducting material and two electrode layers form transistor structures such that the electrodes of the first electrode layer forms source/drain electrode pairs and those of a second electrode layer form the gate electrodes thereof. The source and drain electrodes of a single transistor/memory structure are separated by a narrow recess extending down to the semiconducting layer wherein the transistor channel is provided beneath the recess and with extremely small width, while the source and drain regions are provided beneath the respective source and drain electrodes on either side of the transistor channel. Memory material is provided in the recess and contacts the electrodes of the transistor.