Invention Grant
US06731063B2 Field emission arrays to optimize the size of grid openings and to minimize the occurrence of electrical shorts 失效
场发射阵列,以优化栅格开口的尺寸并最大限度地减少电气短路的发生

  • Patent Title: Field emission arrays to optimize the size of grid openings and to minimize the occurrence of electrical shorts
  • Patent Title (中): 场发射阵列,以优化栅格开口的尺寸并最大限度地减少电气短路的发生
  • Application No.: US10266969
    Application Date: 2002-10-07
  • Publication No.: US06731063B2
    Publication Date: 2004-05-04
  • Inventor: Ammar Derraa
  • Applicant: Ammar Derraa
  • Main IPC: H01J1304
  • IPC: H01J1304
Field emission arrays to optimize the size of grid openings and to minimize the occurrence of electrical shorts
Abstract:
A field emission array includes a dielectric structure with at least two dielectric layers between the cathode and anode grid thereof. The lower dielectric layer is planarized to minimize the occurrence of electrical shorts between the cathode and anode grid of the field emission array. Thus, the upper dielectric layer is substantially free of any electrically conductive defects or imperfections that extend through the lower dielectric layer. In addition, the field emission array includes an array of emitter tips, which are laterally surrounded and may be spaced apart from the dielectric structure. The field emission array may also include a grid over the dielectric structure and the emitter tips, with the emitter tips being exposed through grid openings or apertures.
Information query
Patent Agency Ranking
0/0