发明授权
- 专利标题： Semiconductor integrated circuit device and process for manufacturing
- 专利标题（中）： 半导体集成电路器件及制造工艺
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申请号： US09208879申请日： 1998-12-10
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公开(公告)号： US06734060B2公开(公告)日： 2004-05-11
- 发明人: Yoshitaka Nakamura , Isamu Asano , Keizou Kawakita , Satoru Yamada
- 申请人： Yoshitaka Nakamura , Isamu Asano , Keizou Kawakita , Satoru Yamada
- 优先权： JP9-348823 19971218
- 主分类号： H01L218242
- IPC分类号： H01L218242
摘要：
In a peripheral circuit region of a DRAM, two connection holes 17a, 17b for connecting a first layer line 14 and a second layer line 26 electrically are opened separately in two processes. After forming the connection holes 17a and 17b, plugs 18a and 215a are formed in the connection holes 17a and 17b, respectively.
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