发明授权
US06734473B1 Method of integrated circuit construction with port alignment and timing signal buffering within a common area
失效
集成电路结构的方法，具有端口对准和公共区域内的定时信号缓冲
- 专利标题： Method of integrated circuit construction with port alignment and timing signal buffering within a common area
- 专利标题（中）： 集成电路结构的方法，具有端口对准和公共区域内的定时信号缓冲
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申请号： US09491900申请日： 2000-01-27
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公开(公告)号： US06734473B1公开(公告)日： 2004-05-11
- 发明人: M. Jason Welch , Paul D Nuber
- 申请人： M. Jason Welch , Paul D Nuber
- 主分类号： H01L2710
- IPC分类号： H01L2710
摘要：
The present invention relates to a method of integrated circuit construction in which misaligned ports are linked via an alignment link made up of a wiring trace and signal buffer. The signal buffer and wiring trace are located within a common area of integrated circuit real estate.