A method and device for maintaining data coherency in a semiconductor memory device, having two or more memory chips combined into one chip and operated according to a late select synchronous pipeline type input/output protocol. A method includes the steps of generating first and second bypass summation signals by utilizing a chip block select address signal inputted in a latest write operation and comparison signals obtained from comparison between a latest write address and a current read address; and generating first and second bypass control signals having logic values contrary to each other by utilizing the first and second bypass summation signals and an internal clock signal, wherein a bypass operation is performed in one of read paths associated with the memory chips and a normal read operation is performed through other read paths when all the comparison signals are same.