Invention Grant
US06738251B2 Conductive pattern incorporated in a multilayered substrate, multilayered substrate incorporating a conductive pattern, and a method of fabricating a multilayered substrate 失效
结合在多层基板中的导电图案,包含导电图案的多层基板以及制造多层基板的方法

  • Patent Title: Conductive pattern incorporated in a multilayered substrate, multilayered substrate incorporating a conductive pattern, and a method of fabricating a multilayered substrate
  • Patent Title (中): 结合在多层基板中的导电图案,包含导电图案的多层基板以及制造多层基板的方法
  • Application No.: US09937962
    Application Date: 2001-09-28
  • Publication No.: US06738251B2
    Publication Date: 2004-05-18
  • Inventor: Hiroshi TsuyukiOsamu Hirose
  • Applicant: Hiroshi TsuyukiOsamu Hirose
  • Priority: JP2000-0200003 20000128
  • Main IPC: H01G406
  • IPC: H01G406
Conductive pattern incorporated in a multilayered substrate, multilayered substrate incorporating a conductive pattern, and a method of fabricating a multilayered substrate
Abstract:
The present invention provides a conductive pattern that has low electric resistivity, is superior in adhesion to a substrate and does not cause substrate cracking during plating, a multilayered substrate incorporating such a conductive pattern, and a fabricating method for a multilayered substrate. At first, a conductive composition including a metal powder containing not less than 95 mass % of Ag, a sintering restrainer containing Cr and/or Cr compound, a dielectric loss conditioner containing Mn and/or Mn compound, and a vehicle is prepared. Next, electrodes made of the conductive composition are formed on a plurality of green sheets. The plurality of green sheets formed with the electrodes are then laminated to form a laminated product, whereafter the laminated product is sintered.
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