Invention Grant
- Patent Title: Method of manufacturing a semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US10278793Application Date: 2002-10-24
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Publication No.: US06743704B2Publication Date: 2004-06-01
- Inventor: Masashi Takahashi
- Applicant: Masashi Takahashi
- Priority: JP2002/186767 20020626
- Main IPC: H01L2122
- IPC: H01L2122

Abstract:
A CMOSFET in which a p-type gate electrode and an n-type gate electrode are formed on a silicon substrate. The p-type gate electrode includes, in order, a p-type polycrystalline silicon layer and a tungsten silicide layer. The n-type gate electrode includes, in order, an n-type polycrystaline silicon layer and a tungsten silicide layer. A carbon-containing polycrystalline silicon layer, which is an impurity thermal diffusion prevention layer to suppress the interdiffusion of impurities, is provided between the p-type polycrystalline silicon layer and the tungsten silicide layer.
Public/Granted literature
- US20040002185A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Public/Granted day:2004-01-01
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