发明授权
US06745160B1 Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
失效
使用未解释的符号仿真验证在存在循环的情况下的调度
- 专利标题: Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
- 专利标题(中): 使用未解释的符号仿真验证在存在循环的情况下的调度
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申请号: US09414815申请日: 1999-10-08
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公开(公告)号: US06745160B1公开(公告)日: 2004-06-01
- 发明人: Pranav Ashar , Anand Raghunathan , Subhrajit Bhattacharya , Aarti Gupta
- 申请人: Pranav Ashar , Anand Raghunathan , Subhrajit Bhattacharya , Aarti Gupta
- 主分类号: G06F1750
- IPC分类号: G06F1750
摘要:
A method of checking correctness of scheduling of a circuit where a schedule for the circuit is obtained from a behavioral description. The method comprising extracting loop invariants to determine a sufficient set of acyclic threads when loops are present, performing symbolic simulation to extract the above loop invariants, and proving equivalence of the acyclic threads. Systems, computer systems and computer program products that incorporate the techniques of verification and correctness checking according to the present invention have also been disclosed.
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