Invention Grant
- Patent Title: Barrier layer for copper metallization in integrated circuit fabrication
- Patent Title (中): 集成电路制造中铜金属化的阻挡层
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Application No.: US09982655Application Date: 2001-10-18
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Publication No.: US06747353B2Publication Date: 2004-06-08
- Inventor: Munenori Oizumi , Katsuhiro Aoki , Yukio Fukuda
- Applicant: Munenori Oizumi , Katsuhiro Aoki , Yukio Fukuda
- Main IPC: H01L2348
- IPC: H01L2348

Abstract:
A barrier layer (20, 62) for an integrated circuit structure is disclosed. The barrier layer (20, 62) is a refractory metal silicon compound, such as a refractor metal silicon nitride compound, formed in an amorphous state. The barrier layer (20, 62) has a relatively low composition ratio of silicon, and of nitrogen if present, to provide low resistivity in combination with the high diffusion barrier properties provided by the amorphous state of the film. A disclosed example of the barrier layer (20, 62) is a compound of tantalum, silicon, and nitrogen, formed by controlled co-sputtering of tantalum and silicon in a gas atmosphere including nitrogen and argon. The barrier layer (20) may be used to underlie copper metallization (22), or the barrier layer (62) may be part or all of a lower plate in a ferroelectric memory capacitor (70).
Public/Granted literature
- US20020063337A1 Barrier layer for copper metallization in integrated circuit fabrication Public/Granted day:2002-05-30
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