A transponder (1) and an integrated circuit (4) have at least one signal channel (5, 6, 7), each signal channel (5, 6, 7) having at least two signal processing stages (25, 26, 27, 28, 29, 30, 31) and at least one signal processing stage (26, 27, 29) configured such as to be activatable and deactivatable, while an associated bypass branch (32, 33, 34), which is also activatable and deactivatable, is provided for each activatable and deactivatable signal processing stage (26, 27, 29), and a microcomputer (36) and a control register (37) controllable by the microcomputer, (36) are provided, by means of which each activatable and deactivatable signal processing stage (26, 27, 29) and the associated bypass branch (32, 33, 34) are activatable and deactivatable in counterphase.