发明授权
- 专利标题: Distortion reducing circuit
- 专利标题(中): 失真减少电路
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申请号: US10153630申请日: 2002-05-24
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公开(公告)号: US06753728B2公开(公告)日: 2004-06-22
- 发明人: Yoichi Okubo , Kiyoshi Funada , Masaki Suto , Masato Horaguchi , Toshio Takada , Naoki Hongo
- 申请人: Yoichi Okubo , Kiyoshi Funada , Masaki Suto , Masato Horaguchi , Toshio Takada , Naoki Hongo
- 优先权: JP2001-175647 20010611
- 主分类号: H03F126
- IPC分类号: H03F126
摘要:
A distortion reducing circuit compensates an upper side third-order distortion and a lower side third-order distortion produced by an amplifier for amplifying a fundamental signal including multiple frequency components. The distortion reducing circuit includes a second harmonic reflection coefficient regulation circuit, installed at an output side of the amplifier, for regulating reflection coefficients for multiple frequency components included in a second harmonic signal to have a constant value.
公开/授权文献
- US20030085761A1 Distortion reducing circuit 公开/授权日:2003-05-08
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