发明授权
US06754689B2 Method and apparatus for performing subtraction in redundant form arithmetic
有权
用于以冗余形式算术进行减法的方法和装置
- 专利标题: Method and apparatus for performing subtraction in redundant form arithmetic
- 专利标题(中): 用于以冗余形式算术进行减法的方法和装置
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申请号: US09745697申请日: 2000-12-22
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公开(公告)号: US06754689B2公开(公告)日: 2004-06-22
- 发明人: Bharat Bhushan , Edward Grochowski , John Crawford
- 申请人: Bharat Bhushan , Edward Grochowski , John Crawford
- 主分类号: G06F750
- IPC分类号: G06F750
摘要:
A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing an adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit to generate a valid outcome in redundant form of a subtraction operation. A carry-save adder structure is used in one preferred embodiment of the current invention to perform a subtraction operation A−B, where B is a number represented by one of its valid carry-sum redundant representations. In order to perform the subtraction operation, each of the carry bits and each of the sum bits in a redundant representation of B are complemented and supplied to the carry-save adder. Then a result is corrected by adding an adjustment of three. This adjustment value is incorporated into the result through the carry-save adder circuit. Thus the circuit produces a valid redundant representation for the subtraction operation A−B.
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