发明授权
US06757261B1 GSM transceiver with time division duplexed operations for receiving data, monitoring signal strength and transmitting data during a single time frame 有权
GSM收发器,具有用于在单个时间帧内接收数据,监测信号强度和发送数据的时分双工操作

  • 专利标题: GSM transceiver with time division duplexed operations for receiving data, monitoring signal strength and transmitting data during a single time frame
  • 专利标题(中): GSM收发器,具有用于在单个时间帧内接收数据,监测信号强度和发送数据的时分双工操作
  • 申请号: US09643275
    申请日: 2000-08-22
  • 公开(公告)号: US06757261B1
    公开(公告)日: 2004-06-29
  • 发明人: Christian Volf OlgaardSteve Yeung
  • 申请人: Christian Volf OlgaardSteve Yeung
  • 主分类号: H04J300
  • IPC分类号: H04J300
GSM transceiver with time division duplexed operations for receiving data, monitoring signal strength and transmitting data during a single time frame
摘要:
A Global System for Mobile (GSM) cellular system transceiver with time division duplexed operations for receiving a data signal, monitoring received signal strength and transmitting a data signal during a single time frame. Multiple data registers are used to store the phase lock loop (PLL) frequency control data, e.g., during the last time slot (slot 7) of the prior time frame (or elsewhere in the prior time frame where time permits). Also during slot 7 of the prior time frame, the PLL is programmed using the first data set for the data reception operation to be performed during one or more of the initial time slots (e.g., time slots 0-3) of the present time frame. During the next time slot (e.g., slot 4), the PLL is programmed using the second data set for the signal strength monitoring operation to be performed during that same time slot. During the next time slot (e.g., slot 5), the PLL is programmed using the third data set for the data transmission operation to be performed beginning in that same time slot. By prestoring all three PLL frequency control data sets, such data sets are immediately available when later programming the PLL, thereby reducing the PLL setup time needed prior to each use. Consequently, an integer PLL can be used instead of a fractional PLL while still achieving a sufficiently fast combined setup and lock time, thereby minimizing integrated circuit area and power requirements.
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