- 专利标题： Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same
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申请号： US10122402申请日： 2002-04-12
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公开(公告)号： US06763508B2公开(公告)日： 2004-07-13
- 发明人: Mutsunori Igarashi , Takashi Mitsuhashi
- 申请人： Mutsunori Igarashi , Takashi Mitsuhashi
- 优先权： JPP2001-115780 20010413
- 主分类号： G06F1750
- IPC分类号： G06F1750
摘要：
A layout design system of a semiconductor integrated circuit, comprising: a library information storage unit configured to register a basic via shape list; a technology database storage unit configured to register a list expressing an optimum wire terminating process for each via shape of said basic via shape list registered in said library information storage unit; and a central processing control unit configured to refer to the lists respectively registered in said library information storage unit and said technology database storage unit, select an optimum line processing, and execute a line design.