发明授权
- 专利标题: Method of manufacturing semiconductor device
- 专利标题(中): 制造半导体器件的方法
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申请号: US10392933申请日: 2003-03-21
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公开(公告)号: US06767826B2公开(公告)日: 2004-07-27
- 发明人: Kazuhide Abe
- 申请人: Kazuhide Abe
- 优先权: JP2002-126615 20020426
- 主分类号: H01L214763
- IPC分类号: H01L214763
摘要:
A first insulating layer is formed on first wiring and thereafter an etching resistant film is formed thereon. A lower layer portion of a second insulating layer is formed on the etching resistant film. Upon etching for forming dummy trenches, the rate of etching of the etching resistant film is less than or equal to one-tenth the rate of etching of the insulating layer. Therefore, the etching resistant film functions as an etching stopper and the etching thereof does not proceed to the first insulating layer. Thus, the interval between the corresponding first wiring and a second wiring can be reliably maintained and an increase in parasitic capacitance is hence prevented. An insulator lying within a wiring section is made unnecessary while a dishing phenomenon is prevented, by bottom-up filling of a copper-plated film due to the dummy trenches. Thus, wiring resistance is prevented from increasing.
公开/授权文献
- US20030203619A1 Method of manufacturing semiconductor device 公开/授权日:2003-10-30
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