A prescaler (100) includes a frequency divider (102) having an input node (136) and a divider output (128). The frequency divider is coupled to a clock signal and has a predetermined divisor. Series-coupled delay elements (104, 106, 108) are coupled to the divider output and to the clock signal. Each delay element includes a delayed output (130, 132, 134) and adds a delay equal to the clock period at the delayed output. The prescaler also includes transmission gates (112, 114, 116), each transmission gate coupled between the input node and the delayed output of a corresponding one of the delay elements. When one of the transmission gates is enabled and couples the delayed output of an nth one of the delay elements to the input node, the divider output frequency equals the clock frequency divided by the predetermined divisor plus n.