发明授权
US06772293B2 System and method for optimizing memory bus bandwidth utilization by request classification and ordering
有权
通过请求分类和排序优化内存总线带宽利用率的系统和方法
- 专利标题: System and method for optimizing memory bus bandwidth utilization by request classification and ordering
- 专利标题(中): 通过请求分类和排序优化内存总线带宽利用率的系统和方法
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申请号: US09748979申请日: 2000-12-27
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公开(公告)号: US06772293B2公开(公告)日: 2004-08-03
- 发明人: Ramacharan Sundararaman , Gustavo P. Espinosa , JunSeong Kim , Ryan L. Carlson
- 申请人: Ramacharan Sundararaman , Gustavo P. Espinosa , JunSeong Kim , Ryan L. Carlson
- 主分类号: G06F1200
- IPC分类号: G06F1200
摘要:
Mechanisms for improving the efficiency of bus-request scheduling are provided. In a read-write segregation mechanism the type of a selected entry in a buffer is determined. If the type of the selected entry matches the type of the last issued entry, or if there are no further entries in the buffer that match the last issued entry, the request is issued to the system bus. A temporal ordering mechanism associates a request sent to a buffer with an identifier, the identifier designating a time at which the request was originally generated. The request identifier is modified when a prior request is issued, and thereby reflects a history of prior issuances. A request is issued when the historical information recorded in the identifier indicates that the request is the earliest-issued pending request in the buffer. A third mechanism for increasing the efficiency of bus request scheduling in a buffer includes segregating lower priority cache eviction requests in a separate write-out section of the buffer. Request entries in the write-out section are issued to a system bus only when there are no pending entries in a bus queue.
公开/授权文献
- US20020083277A1 Mechanisms to improve bus-request scheduling 公开/授权日:2002-06-27
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