发明授权
- 专利标题: Semiconductor integrated circuit and a burn-in method thereof
- 专利标题(中): 半导体集成电路及其老化方法
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申请号: US10309183申请日: 2002-12-04
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公开(公告)号: US06777997B2公开(公告)日: 2004-08-17
- 发明人: Shigemitsu Tahara , Daisuke Katagiri , Takeshi Shimanuki , Masashi Oshiba
- 申请人: Shigemitsu Tahara , Daisuke Katagiri , Takeshi Shimanuki , Masashi Oshiba
- 优先权: JP2002-009500 20020118
- 主分类号: H03L500
- IPC分类号: H03L500
摘要:
The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other. The second circuit has a plurality of level shift circuits capable of shifting the level of an output of the first circuit in accordance with an operation voltage of the second circuit, a plurality of external output buffers receiving outputs of the level shift circuits, bypasses for bypassing an input of a predetermined level shift circuit to an input of a predetermined external output buffer, and a selecting circuit for selecting connection of either the predetermined level shift circuit or a bypass to an input of the predetermined external output buffer. In a use form in which the first and second circuits operate with a low voltage, the bypass is selected. In high-voltage operation and burn-in, the level shift circuits are selected.
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