Invention Grant
- Patent Title: Method of reducing device parasitic capacitance using underneath crystallographically selective wet etching
- Patent Title (中): 使用晶体选择性湿蚀刻下降器件寄生电容的方法
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Application No.: US10271246Application Date: 2002-10-15
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Publication No.: US06780702B2Publication Date: 2004-08-24
- Inventor: Myoung Hoon Yoon , Kyoung Hoon Yang
- Applicant: Myoung Hoon Yoon , Kyoung Hoon Yang
- Priority: KR2001-65567 20011024
- Main IPC: H01L218249
- IPC: H01L218249

Abstract:
When InP DHBTs are located in parallel to a crystallographical direction of , there are several advantages in the aspect of device property such as reliability. But, in case of a direction parallel to a general , there exists the limitation in reducing base-collector parasitic capacitance only by collector over-etching technique due to poor lateral-etching characteristic of the InP collector. To overcome such a problem mentioned above and improve device performance, the present invention provides a method of reducing parasitic capacitance using underneath crystallographically selective wet etching, thereby providing a self-alignable, structurally stable device.
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