A SIMD processor includes plural processor elements (PEs) each having a processing unit for data processing, a register for holding data to be processed or already processed by the processing unit, a data transfer bus interconnecting with other PEs, and a register controller for inputting a read or write signal to the register. Read and write processing steps in the processor are carried out by the register controller in response to the signals which are sent form the register controller and inputted into a register of specific processor elements responding to an addressing signal from an external interface. The processor is capable of transferring data directly to a specific processor element, thereby achieving higher speeds of data transfer and resultant data processing and makes flexible use of registers to thereby attain efficient data processing utilizing arbitrary combinations of the register depending on bit width of the data.