发明授权
US06791379B1 Low jitter high phase resolution PLL-based timing recovery system
有权
低抖动高相位分辨率基于PLL的定时恢复系统
- 专利标题: Low jitter high phase resolution PLL-based timing recovery system
- 专利标题(中): 低抖动高相位分辨率基于PLL的定时恢复系统
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申请号: US09456230申请日: 1999-12-07
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公开(公告)号: US06791379B1公开(公告)日: 2004-09-14
- 发明人: Myles Wakayama , Stephen A. Jantzi , Kwang Young Kim , Yee Ling Felix Cheung , Ka Wai Tong
- 申请人: Myles Wakayama , Stephen A. Jantzi , Kwang Young Kim , Yee Ling Felix Cheung , Ka Wai Tong
- 主分类号: H03L706
- IPC分类号: H03L706
摘要:
A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.