Reduced gate leakage current in thin gate dielectric CMOS integrated circuits

发明授权

US06791383B2 Reduced gate leakage current in thin gate dielectric CMOS integrated circuits 有权

标题翻译：在薄栅极介质CMOS集成电路中降低栅极漏电流

请登陆查看更多内容

专利标题： Reduced gate leakage current in thin gate dielectric CMOS integrated circuits
专利标题（中）： 在薄栅极介质CMOS集成电路中降低栅极漏电流
申请号： US10265850

申请日： 2002-10-07
公开(公告)号： US06791383B2

公开(公告)日： 2004-09-14
发明人: Amitava Chatterjee
申请人： Amitava Chatterjee
主分类号： H03L706
IPC分类号： H03L706

Reduced gate leakage current in thin gate dielectric CMOS integrated circuits

摘要：

The invention describes a method for reducing the leakage current in thin gate dielectric MOS capacitors in integrated circuits. A bias voltage is determined for the MOS capacitor such that the capacitor area and leakage current constraints are satisfied. The MOS capacitor is not biased in inversion.

摘要（中）：

本发明描述了一种用于减小集成电路中的薄栅介质MOS电容器中的漏电流的方法。确定MOS电容器的偏置电压，使得满足电容器面积和漏电流限制。 MOS电容器在反相中没有偏置。

公开/授权文献

US20040067600A1 Reduced gate leakage current in thin gate dielectric CMOS integrated circuits 公开/授权日：2004-04-08

信息查询

Espacenet