发明授权
- 专利标题: Non-volatile memory read circuit with end of life simulation
- 专利标题(中): 非易失性存储器读取电路,具有寿命终止模拟
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申请号: US10431320申请日: 2003-05-06
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公开(公告)号: US06791880B1公开(公告)日: 2004-09-14
- 发明人: Kazuhiro Kurihara , Binh Quang Le , Pau-Ling Chen , Darlene Hamilton , Edward Hsia
- 申请人: Kazuhiro Kurihara , Binh Quang Le , Pau-Ling Chen , Darlene Hamilton , Edward Hsia
- 主分类号: G11C1606
- IPC分类号: G11C1606
摘要:
A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.
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