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US06794704B2 Method for enhancing electrode surface area in DRAM cell capacitors 失效
提高DRAM单元电容器电极表面积的方法

Method for enhancing electrode surface area in DRAM cell capacitors
Abstract:
Lower electrodes of capacitors composed of a texturizing underlayer and a conductive material overlayer are provided. The lower electrodes have an upper roughened surface. In one embodiment, the texturizing layer is composed of porous or relief nanostructures comprising a polymeric material, for example, silicon oxycarbide. In another embodiment, the texturizing underlayer is in the form of surface dislocations composed of annealed first and second conductive metal layers, and the conductive metal overlayer is agglomerated onto the surface dislocations as nanostructures in the form of island clusters.
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