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US06794912B2 Multi-phase clock transmission circuit and method 失效
多相时钟传输电路及方法

  • 专利标题: Multi-phase clock transmission circuit and method
  • 专利标题(中): 多相时钟传输电路及方法
  • 申请号: US10361610
    申请日: 2003-02-11
  • 公开(公告)号: US06794912B2
    公开(公告)日: 2004-09-21
  • 发明人: Takashi HirataToru Iwata
  • 申请人: Takashi HirataToru Iwata
  • 优先权: JP2002-040158 20020218
  • 主分类号: H03D324
  • IPC分类号: H03D324
Multi-phase clock transmission circuit and method
摘要:
A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal. Signals output from the plurality of delay elements are used as signals constituting the multi-phase clock.
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