发明授权
US06795003B2 Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's
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在Σ-ΔDAC中实现动态元件匹配的高效实现
- 专利标题: Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's
- 专利标题(中): 在Σ-ΔDAC中实现动态元件匹配的高效实现
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申请号: US10354159申请日: 2003-01-30
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公开(公告)号: US06795003B2公开(公告)日: 2004-09-21
- 发明人: Minsheng Wang , Anil Tammineedi
- 申请人: Minsheng Wang , Anil Tammineedi
- 主分类号: H03M300
- IPC分类号: H03M300
摘要:
A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ±1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.
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