Invention Grant
- Patent Title: Voltage reference generation circuit and power source incorporating such circuit
- Patent Title (中): 电压基准信号生成电路和并入电路的电源
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Application No.: US10376277Application Date: 2003-03-03
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Publication No.: US06798278B2Publication Date: 2004-09-28
- Inventor: Yoshinori Ueda
- Applicant: Yoshinori Ueda
- Priority: JP2000-189343 20000623; JP2000-279070 20000914
- Main IPC: G05F324
- IPC: G05F324

Abstract:
A voltage reference generation circuit is disclosed including a voltage reference generating stage and a voltage reference output stage, in which a depletion-mode MOS transistor and an enhancement-mode MOS transistor are connected in series, and the junction formed between these MOS transistors serves as an output terminal for outputting a voltage to be input to the voltage reference output stage. In the output stage, two enhancement-mode MOS transistors having the same channel dopant profile are connected in series between a power source and the ground, the gate of one MOS transistor is connected to the output terminal of the generating stage, the gate and drain of the other MOS transistor are interconnected, and the junction formed between these MOS transistors serves as an output terminal for a voltage reference. In addition, each of the enhancement-mode MOS transistors is provided with a floating gate having a different threshold voltage depending on, the coupling coefficient between the floating gate and a gate, the amount of charge input to the floating gate, the kind of dielectric material included in the gate, or the thickness of a gate oxide layer, which is suitably utilized to supply reference voltages with improved stability to fluctuations in operating temperatures or processing parameters.
Public/Granted literature
- US20030146785A1 Voltage reference generation circuit and power source incorporating such circuit Public/Granted day:2003-08-07
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