发明授权
US06806550B2 Evaluation configuration for semiconductor memories 失效
半导体存储器的评估配置

  • 专利标题: Evaluation configuration for semiconductor memories
  • 专利标题(中): 半导体存储器的评估配置
  • 申请号: US10244258
    申请日: 2002-09-16
  • 公开(公告)号: US06806550B2
    公开(公告)日: 2004-10-19
  • 发明人: Kurt HoffmannOskar Kowarik
  • 申请人: Kurt HoffmannOskar Kowarik
  • 优先权: DE10145556 20010914
  • 主分类号: H01L2900
  • IPC分类号: H01L2900
Evaluation configuration for semiconductor memories
摘要:
An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.
公开/授权文献
信息查询
0/0