发明授权
US06808981B2 Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI
失效
用于制造具有双门控垂直MOSFET和自对准STI的6F2沟槽DRAM单元的方法
- 专利标题: Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI
- 专利标题(中): 用于制造具有双门控垂直MOSFET和自对准STI的6F2沟槽DRAM单元的方法
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申请号: US10375654申请日: 2003-02-27
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公开(公告)号: US06808981B2公开(公告)日: 2004-10-26
- 发明人: Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
- 申请人: Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
- 主分类号: H01L218242
- IPC分类号: H01L218242
摘要:
A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.
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