Disclosed are a multi-stage A/D converter with pipeline structure and a coding method for designing the same, wherein the multi-stage A/D converter comprises a sample-and-hold unit for receiving, sampling and holding analog input signals, a converter section having a plurality of stages for receiving an output of the sample-and-hold unit and generating digital data with a predetermined number of bits, and a correction circuit for correcting an offset error by overlapping an LSB of data of a previous stage and an MSB of data of a subsequent stage when an offset error is caused in the previous stage, receiving the digital data from each stage of the converter section, and outputting digital output data, wherein a second stage of the converter section has an error correction bit for correcting an error caused in a first stage but a third and other stages coming after the third stage do not have an error correction bit.