发明授权
- 专利标题: System latency levelization for read data
- 专利标题(中): 读取数据的系统延迟级别化
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申请号: US10720183申请日: 2003-11-25
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公开(公告)号: US06851016B2公开(公告)日: 2005-02-01
- 发明人: Jeffery W. Janzen , Brent Keeth , Kevin J. Ryan , Troy A. Manning , Brian Johnson
- 申请人: Jeffery W. Janzen , Brent Keeth , Kevin J. Ryan , Troy A. Manning , Brian Johnson
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Dickstein Shapiro Morin & Oshinsky LLP
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G11C7/10 ; G11C7/22 ; G11C11/407
摘要:
In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
公开/授权文献
- US20040107326A1 System latency levelization for read data 公开/授权日:2004-06-03
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