Invention Grant
- Patent Title: Hardening logic devices
- Patent Title (中): 硬化逻辑器件
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Application No.: US10426248Application Date: 2003-04-28
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Publication No.: US06864712B2Publication Date: 2005-03-08
- Inventor: Deepak Agarwal , Parvesh Swami
- Applicant: Deepak Agarwal , Parvesh Swami
- Applicant Address: GB
- Assignee: STMicroelectronics Limited
- Current Assignee: STMicroelectronics Limited
- Current Assignee Address: GB
- Agency: Jenkens & Gilchrist, P.C.
- Main IPC: G11C11/412
- IPC: G11C11/412 ; H03K19/177

Abstract:
The present invention is concerned with a method and apparatus for hardening logic devices. The logic device has a plurality of memory cells forming an array connected by data lines and clock lines, and the device having a further connecting line. The method comprising: receiving data on said data lines for configuring each of the memory cells. Storing data in each of the memory cells by enabling at least one of the clock lines and when the desired data has been stored, hardening the array to fix the data by selectively connecting the data and clock lines to the further line.
Public/Granted literature
- US20040212394A1 Hardening logic devices Public/Granted day:2004-10-28
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