发明授权
- 专利标题： Methods of forming integrated circuit memory devices that include a plurality of landing pad holes that are arranged in a staggered pattern and integrated circuit memory devices formed thereby
- 专利标题（中）： 形成集成电路存储器件的方法包括以交错图案布置的多个着陆焊盘孔和由此形成的集成电路存储器件
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申请号： US10442481申请日： 2003-05-21
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公开(公告)号： US06890841B2公开(公告)日： 2005-05-10
- 发明人: Kyu-hyun Lee , Tae-young Chung , Chang-hyun Cho , Yang-keun Park , Sang-bum Kim
- 申请人： Kyu-hyun Lee , Tae-young Chung , Chang-hyun Cho , Yang-keun Park , Sang-bum Kim
- 申请人地址： KR
- 专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人地址： KR
- 代理机构： Myers Bigel Sibley & Sajovec
- 优先权： KR10-2002-0034996 20020621
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L21/02 ; H01L21/768 ; H01L21/822 ; H01L21/8242 ; H01L27/04 ; H01L27/108 ; H01L21/20 ; H01L29/94
摘要：
An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.