发明授权
- 专利标题: Counter circuit
- 专利标题(中): 计数器电路
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申请号: US10329425申请日: 2002-12-27
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公开(公告)号: US06895070B2公开(公告)日: 2005-05-17
- 发明人: Hirokazu Kobayashi , Yuji Tanaka
- 申请人: Hirokazu Kobayashi , Yuji Tanaka
- 申请人地址: JP Osaka
- 专利权人: Sharp Kabushiki Kaisha
- 当前专利权人: Sharp Kabushiki Kaisha
- 当前专利权人地址: JP Osaka
- 代理机构: Birch, Stewart, Kolasch & Birch, LLP.
- 优先权: JP2001-400930 20011228; JP2002-107056 20020409
- 主分类号: H03K23/00
- IPC分类号: H03K23/00 ; H03K21/00 ; H03K23/66
摘要:
The counter circuit comprises the initial value single port RAM having N initial value registers allocated for memorizing N initial values, the counter register single port RAM having N counter registers allocated for memorizing N counting values, and the control circuit for performing a counting operation for each counter register. The control circuit performs the counting operation for each counter register on a time division basis by using a single arithmetic unit.
公开/授权文献
- US20030123602A1 Counter circuit 公开/授权日:2003-07-03