发明授权
- 专利标题： Method and structures for reduced parasitic capacitance in integrated circuit metallizations
- 专利标题（中）： 集成电路金属化中减小寄生电容的方法和结构
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申请号： US10178172申请日： 2002-06-21
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公开(公告)号： US06909196B2公开(公告)日： 2005-06-21
- 发明人: Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
- 申请人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 代理机构： Knobbe Martens Olson & Bear LLP
- 主分类号： H01L23/485
- IPC分类号： H01L23/485 ; H01L23/522 ; H01L23/48 ; H01L23/52 ; H01L29/40
摘要：
A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
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