- 专利标题: Semiconductor memory device using only single-channel transistor to apply voltage to selected word line
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申请号: US10607153申请日: 2003-06-27
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公开(公告)号: US06912157B2公开(公告)日: 2005-06-28
- 发明人: Hiroshi Nakamura , Kenichi Imamiya
- 申请人: Hiroshi Nakamura , Kenichi Imamiya
- 申请人地址: JP Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Kawasaki
- 代理机构: Banner & Witcoff, Ltd.
- 优先权: JP2000-173715 20000609; JP2000-330972 20001030
- 主分类号: G11C11/413
- IPC分类号: G11C11/413 ; G11C16/04 ; G11C16/06 ; G11C16/08 ; H01L27/115
摘要:
A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.
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