发明授权
- 专利标题: Shift register for pulse-cut clock signal
- 专利标题(中): 移位寄存器用于脉冲切割时钟信号
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申请号: US10118129申请日: 2002-04-09
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公开(公告)号: US06928135B2公开(公告)日: 2005-08-09
- 发明人: Yasushi Sasaki , Tetsuo Morita
- 申请人: Yasushi Sasaki , Tetsuo Morita
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权: JP2001-116010 20010413
- 主分类号: G02F1/133
- IPC分类号: G02F1/133 ; G09G3/20 ; G09G3/30 ; G09G3/36 ; G11C8/04 ; G11C19/00 ; G11C19/28
摘要:
When a voltage level of a pulse-cut first clock signal inputted to a first clock terminal is reversed in the state where a first transistor is turned on and a second transistor is turned off, an anti-reversal circuit including a seventh transistor and an eighth transistor supplies a high voltage VDD to a node n2. In this way, a floating state of the node n2 is avoided, and the voltage level of the node n2 is prevented from being reversed. Accordingly, the second transistor will not be turned on in the interval, whereby electric potential of an output signal is stably maintained.
公开/授权文献
- US20020150199A1 Shift register for pulse-cut clock signal 公开/授权日:2002-10-17